With the integration of integrated circuits increasing, the manufacturing techniques of the integrated circuits continually develop to smaller critical dimension (CD). However, photolithography process has become a critical bottleneck in limiting the development of integrated circuits to smaller CD. The main principle of the photolithography process is to project a designed layout of an integrated circuit on a mask onto a wafer through light source. However, with the decreasing of CD, optical distortion and abnormal shape of an image projected on the wafer make it difficult to achieve a desired CD of a projected pattern with small CD, thus yield of the photolithography process is affected. Optical proximity correction (OPC) is applied to compensate for these deformations, so that the image finally projected on the wafer can get a better CD control.
Performing OPC to a layout is based on sampling of the layout, so that discrete sampling results can be acquired. The sampling quality of the layout to be corrected has a direct impact on the OPC result.
However, accuracy and efficiency of sampling of a layout to be corrected in a conventional technology needs to be improved.